1. Field of the Invention
The present invention relates to memory architectures, and more particularly, the present invention relates to memory architectures for cache memories to reduce the average current required for read or write operations.
2. Art Background
In many data processing systems, it is common to utilize a high speed buffer memory, referred to as a "cache", coupled to a central processing unit (CPU) to improve the average memory access time for the processor. The use of the cache is based upon the premise that over time, a data processing system will access certain localized areas of memory with high frequency. The cache typically contains a subset of the complete data set disposed in the main memory, and can be accessed very quickly by the CPU without the necessity of reading the data locations in the main memory.
The use of a cache adds considerable complexity to a data processing system and substantially increases system cost and power requirements. In modern computer systems, it is critical to minimize power requirements whenever possible. The minimization of power requirements increases system efficiency, and, in the case of portable computer systems, prolongs battery life.
As will be described, the present invention provides a memory architecture, having particular application to cache memories, which reduces the average current for a read operation significantly. The present invention discloses apparatus and methods for providing an improved cache memory architecture in a computer system.